Senior Physical Design Methodology Engineer, PPA Fusion Compiler

Job Description

NVIDIA is seeking a Senior Physical Design Methodology Engineer to join their Networking Silicon engineering team and work on developing high-speed communication devices.

Requirements

• MS in Electrical or Computer Engineering (or equivalent experience)
• Minimum 5 years' experience in Physical Design Engineering
• Familiarity with chip design aspects such as Floor planning, Clock and Power distribution, Place and Route, Integration and Verification
• Strong background in physical design with convergence in timing/EM/IR for best PPA
• Solid understanding of industry-standard PnR tools and analysis tools, capable of scripting to check and improve PPA

Responsibilities

• Develop efficient physical design methodologies for implementing graphics processors and SOCs
• Participate in developing flow and tool methodologies for P&R, timing analysis and closure, convergence in IR/Signal-EM, power and noise analysis
• Provide extensive timing knowledge to support implementation convergence
• Analyze data and develop algorithmic solutions for PPA check and improvement

Benefits

• Multiple relocation packages
• Two weeklong shutdowns (mid-summer and year-end) in the US (in addition to PTO)
• 8-week parental leave
• 9 Employee Resource Groups
• Annual bonus offering
• Flexible work arrangements
• Up to 6% 401K matching