Senior ASIC Power Integrity Engineer

Job Description

NVIDIA is seeking a Senior ASIC Power Integrity Engineer to contribute to the development of the networking product line.

Requirements

• BSEE / MSEE or equivalent experience
• 5+ years of experience in power integrity engineering
• Proven experience in analyzing, mitigating, and optimizing power integrity in high-performance computing or networking hardware
• Proficiency with industry-standard PI tools such as Cadence, Ansys, or other EM simulation tools
• Strong communication and teamwork skills
• Ability to thrive in a dynamic, fast-paced environment
• Proficiency using Python, Perl, Tcl, Make scripting

Responsibilities

• Ensuring robust power integrity in physical design to optimize power delivery
• Designing and optimizing physical design solutions for power integrity
• Performing power integrity analysis and mitigation
• Serving as the focal point for PI for partition owners
• Collaborating with hardware and design teams on power delivery strategies
• Applying tools and flow in advanced technology to achieve project development goals

Benefits

• Multiple relocation packages
• Two weeklong shutdowns (mid-summer and year-end) in the US (in addition to PTO)
• 8-week parental leave
• 9 Employee Resource Groups
• Annual bonus offering
• Flexible work arrangements
• Up to 6% 401K matching