SoC Physical Design Engineer, PnR

Job Description

Seeking a seasoned Physical Design technical leader with deep expertise in high-performance & low-power design to work on efficient chip and IP physical architecture.

Requirements

• Minimum BS and 10+ years of relevant industry experience
• Knowledgeable in partition level P&R implementation including floorplanning, clock & power distribution, timing closure, and physical & electrical verification
• Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ
• Strong interpersonal skills
• Recent successful tapeouts in deep submicron technology

Responsibilities

• Responsible for all aspects of physical design implementation from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off
• Collaborate to drive methodologies and 'best-known methods' to streamline PD work and develop guidelines and checklists
• Be the primary technical contact for your focus area and solve challenging timing closure issues, area & power optimization