SoC Physical Design Engineer, PnR

Job Description

Seeking a seasoned Physical Design technical leader with deep expertise in high-performance & low-power design to work on chip and IP physical architecture.

Requirements

• Minimum BS and 3+ years of relevant industry experience
• Knowledgeable in partition level P&R implementation including floorplanning, clock & power distribution
• Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ
• Strong interpersonal skills

Responsibilities

• Responsible for all aspects of physical design implementation from RTL2GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off
• Collaborate to drive methodologies and 'best-known methods' to streamline PD work
• Develop guidelines and checklists
• Primary technical contact for focus area, solving timing closure issues, area & power optimization