SoC Physical Design Engineer, PnR

Job Description

Join Apple in a visible role responsible for the physical implementation of design partition(s) for a highly complex SOC utilizing innovative process technology.

Requirements

• Minimum BS and 8+ years of relevant industry experience
• Ability to adhere to stringent schedule and die size requirements
• Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ
• Experience with sub 10nm tech nodes
• Strong communication skills
• Experience with partition level P&R implementation including floorplanning, clock and power distribution, timing closure, physical and electrical verification
• Knowledge of physical design construction and analysis flows and methodology
• Experience with industry standard tools, understanding their capabilities and underlying algorithms
• Post silicon debug skills and DFT, ATPG, ATE knowledge

Responsibilities

• Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle
• Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals
• Timing, physical and electrical verification and driving the signoff closure for the partitions
• Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution