PLL/Clocking Design Engineer

Job Description

Develop cutting-edge frequency synthesizers for various applications at Apple to maintain innovation and market leadership.

Requirements

• BSEE required or years of relevant experience
• MSEE preferred
• Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design
• Deep understanding of clocking fundamentals
• Skilled in developing System Verilog models
• Exceptional focus on problem-solving
• Demonstrated leadership skills and a growth mindset

Responsibilities

• Develop cutting-edge frequency synthesizers for various applications
• Contribute to maintaining Apple's leadership in innovation and market presence
• Explore new architectural performance through behavioral simulations
• Collaborate effectively within a team environment