PLL/Clocking Design Engineer

Job Description

Develop cutting-edge frequency synthesizers for various applications to maintain Apple's leadership in innovation and market presence.

Requirements

• BSEE with at least 10 years of relevant experience
• Demonstrated proficiency in PLL/FLL and frequency synthesis architecture and circuit design
• Deep understanding of clocking fundamentals and phase noise
• Skilled in developing System Verilog models and performing behavioral simulations
• Exceptional attention to detail and problem-solving skills
• History of innovation and self-directed learning
• Outstanding teamwork capabilities and productivity skills

Responsibilities

• Develop cutting-edge frequency synthesizers for applications like Compute, SoC, SerDes, and Cellular technologies
• Contribute to maintaining Apple's leadership in innovation and market presence
• Set new standards in the tech industry
• Work on high-quality, innovative hard IPs
• Adapt to the complexity of SOC/PHY designs and tight production schedules
• Collaborate with a team of exceptional individuals