SoC Power Flow Methodology Engineer

Job Description

As a Power Flow Methodology Engineer, you’ll deliver new automated solutions and capabilities for the Silicon Engineering Power team to build chips that are more power efficient than ever before.

Requirements

• Minimum requirement of a Bachelors Degree (preferably in a relevant field - EE)
• Good understanding of VLSI designs and SOC design flows
• Strong passion for scripting and applying low-power domain-specific knowledge to create new software solutions
• Solid understanding and proven track record using modern software testing and development practices
• Good written/verbal communications skills are required

Responsibilities

• Development and enhancement of low-power flows
• Provide designers new capabilities in terms of power domains
• Craft low-power methodologies across a wide variety of future technologies
• Create flows and tools related to power analysis, optimization and verification
• Communicate with the design team to answer questions and drive issues to resolution