Formal Verification Engineer

Job Description

As a formal verification engineer at Apple, you will be responsible for working on the complete formal verification for single or multiple design blocks and IPs, ensuring high-quality functional products are delivered to millions of customers quickly.

Requirements

• BS degree
• Minimum of 10 years of relevant industry experience in silicon validation software engineering or related field
• Hands-on experience with VLSI and digital logic design and verification techniques
• Interest in learning and becoming an expert in SoC, CPU, GPU, or Cellular designs
• Detail-oriented approach and desire to overcome challenges
• Knowledge and experience in interpreting hardware specifications
• Proficiency in any scripting language with excellent debugging skills
• Excellent interpersonal skills

Responsibilities

• Develop formal micro-architecture specifications
• Develop comprehensive formal verification test plans
• Prove properties of the design and find design bugs
• Craft novel and creative solutions for verifying complex design micro-architectures
• Develop and implement reusable and optimized formal models and verification codebase
• Architect correct-by-construction design methodologies for improved formal verification efficiency and productivity