Senior ASIC Verification Engineer

Job Description

The NVIDIA Clocks Team is seeking a Senior ASIC Verification engineer with expertise in Design Verification to ensure high-quality clocking and reset logic for a range of products including Data Centers, Consumer graphics, Self-driving cars, and artificial intelligence applications.

Requirements

• BS or MS in EE/ECE or equivalent experience
• 5+ years of relevant industry work experience
• Good understanding of Logic Design and Architecture
• Expertise in industry-standard verification flows like SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, X prop, etc.
• Experience in block level and system-level verification
• Strong coding skills in System Verilog, scripting languages (Perl/python) and C++
• Ability to collaborate and work with multiple groups
• Prior experience in implementing Test plans for pre-silicon platforms
• Understanding of DFT/IST is optional

Responsibilities

• Own validation of Clocking structures in Tegra and GPU products from start to finish
• Develop scalable solutions for Sophisticated problems that work across platforms
• Hands-on use of industry-standard tools and state-of-the-art verification methodologies
• Partner closely with clocks architecture and design team to validate clocks design
• Coordinate with internal and external teams across different time zones

Benefits

• Multiple relocation packages
• Two weeklong shutdowns (mid-summer and year-end) in the US (in addition to PTO)
• 8-week parental leave
• 9 Employee Resource Groups
• Annual bonus offering
• Flexible work arrangements
• Up to 6% 401K matching