Senior High-Performance ASIC Timing Engineer

Job Description

NVIDIA is seeking a motivated individual to join their dynamic and growing team to work on timing closure plans for high-performance IPs for CPU, GPU, and SOC designs.

Requirements

• BS or MS in Electrical or Computer Engineering
• 5+ years of experience with BS or 3+ years of experience with MS in ASIC Design and Timing
• Hands-on experience in STA tools, ECO implementation, and timing closure of high-speed designs
• Strong background in timing constraints generation, clocking, process variations, and signal integrity
• Proficiency in programming and scripting languages such as Perl, Tcl, Python
• Familiarity with logic synthesis, equivalence checking, and methodology/tools
• Strong interpersonal and communication skills with the ability to collaborate with cross-functional teams
• Strong understanding of timing and physical design fundamentals

Responsibilities

• Develop and execute timing closure plans for high-performance IPs
• Own static timing analysis and convergence of designs
• Set up timing constraints, perform timing analysis and closure, ECO implementation, and timing methodologies
• Find tradeoffs and balance between power, area, congestions, etc.
• Develop new methodologies/flows and workflows to aid timing convergence

Benefits

• Multiple relocation packages
• Two weeklong shutdowns (mid-summer and year-end) in the US (in addition to PTO)
• 8-week parental leave
• 9 Employee Resource Groups
• Annual bonus offering
• Flexible work arrangements
• Up to 6% 401K matching