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Senior Circuit Characterization Engineer

NVIDIA Corporation

3/27/2025

US, CA, Santa Clara

Full-time

Salary: $136,000 - $264,500


Job Description

Join NVIDIA's Silicon Solutions Engineering Team to productize NVIDIA's chips into groundbreaking consumer, professional, server, mobile, and automotive solutions.

Requirements

  • BS or MS degree in EE/CE or equivalent experience
  • 5+ years of relevant experience in silicon bring-up and post silicon validation activities
  • Excellent problem-solving, collaborative, and interpersonal skills
  • Experience working with offshore teams preferred
  • Knowledge of chip and board level dI/dt analysis/mitigation techniques and board PDN design background is highly desirable
  • Hands-on experience with silicon bringup, frequency and power characterization, Tester to System correlation, lab equipment (oscilloscopes, multimeters, DAQ, Spectrum Analyzers)
  • Deep understanding of product binning methods, optimization techniques, methods, trade-off analysis and tools for data analysis and statistics
  • Exposure to critical path analysis, power analysis, process technologies, transistor/device physics, silicon reliability and aging mechanisms
  • Familiarity with Python, C/C++, tool and script development
  • Background with power supply and substrate noise analysis and mitigation
  • Exposure to digital design, circuit analysis, computer architecture, BIOS, drivers, and software applications

Responsibilities

  • Participate in silicon bringup & post-silicon characterization of new silicon to optimize performance, power, yield, and quality
  • Build methodologies to characterize Analog, digital and Mixed Signal circuits, silicon features, correlate silicon behavior with simulations
  • Design tools to improve execution efficiency to work on multiple products simultaneously
  • Find creative solutions to complex silicon and system level problems, lead show-stopper bugs to enable product shipment
  • Work closely with other engineering teams to determine coverage needs and constraints
  • Drive design improvements for future products based on lab findings
  • Lead and Mentor Junior Engineers and Interns

Benefits

  • Multiple relocation packages
  • Two weeklong shutdowns (mid-summer and year-end) in the US (in addition to PTO)
  • 8-week parental leave
  • 9 Employee Resource Groups
  • Annual bonus offering
  • Flexible work arrangements
  • Up to 6% 401K matching
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