ASIC Design Engineer - New College Grad 2025

Job Description

Join our digital logic interconnect design team to work on implementing logic for next-generation GPUs and SOCs enabling high-performance interconnect for various applications.

Requirements

• Bachelors Degree in EE, CS or CE
• Experience in coding PCIE PL/DL logic or lower layers of the OSI stack
• In-depth understanding of physical design
• Strong working knowledge of Verilog or System Verilog
• Strong collaboration and communication skills

Responsibilities

• Micro architecting the next generation of PCIE PL and DL
• Implementing readable, high-performance, area and power efficient RTL
• Collaborating with architects, external partners, software engineers, and circuit designers
• Providing design documentation, triaging and debugging functional and performance bugs

Benefits

• Multiple relocation packages
• Two weeklong shutdowns (mid-summer and year-end) in the US (in addition to PTO)
• 8-week parental leave
• 9 Employee Resource Groups
• Annual bonus offering
• Flexible work arrangements
• Up to 6% 401K matching