Senior DFT Engineer

Job Description

Design-for-Test Engineering position at NVIDIA involving crafting creative solutions for DFT architecture, verification, and post-silicon validation on complex semiconductor chips.

Requirements

• BSEE (or equivalent experience) with 5+ years, MSEE with 3+ years, or PhD in DFT or related domains
• Experience in defining scan test plans, BIST, fault modeling, ATPG, fault simulation
• Analytical skills in verification and validation of test patterns on complex designs
• Exposure to RTL & clocks design, STA, place-n-route, power management
• Experience in Silicon debug and bring-up on ATE
• Strong programming and scripting skills in Perl, Python, or Tcl
• Excellent written and oral communication skills

Responsibilities

• Implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST, and scan compression
• Developing and deploying DFT methodologies for next-generation products
• Mentoring junior engineers on test designs and trade-offs

Benefits

• Multiple relocation packages
• Two weeklong shutdowns (mid-summer and year-end) in the US (in addition to PTO)
• 8-week parental leave
• 9 Employee Resource Groups
• Annual bonus offering
• Flexible work arrangements
• Up to 6% 401K matching